E aʻo e pili ana ma o ke kilika ma o (TSV) a ma ke aniani ma o ka ʻenehana (TGV) ma hoʻokahi ʻatikala

ʻO ka ʻenehana Packaging kekahi o nā kaʻina hana nui i ka ʻoihana semiconductor. E like me ke ʻano o ka puʻupuʻu, hiki ke hoʻokaʻawale ʻia i loko o ka puʻupuʻu socket, ka puʻupuʻu mauna o ka honua, ka pūʻolo BGA, ka nui o ka puʻupuʻu (CSP), ka pūʻulu module chip hoʻokahi (SCM, ke āpau ma waena o nā wili ma ka papa kaapuni paʻi (PCB) a me ka hui 'ana o ka papa pad matches (IC), multi-chip module package (MCM, hiki ke hoʻohui i nā'āpana heterogeneous), wafer level package (WLP, me ka fan-out wafer level package (FOWLP), micro surface mount. nā ʻāpana (microSMD), a me nā mea ʻē aʻe), ʻekolu-dimensional pūʻolo (micro bump interconnect package, TSV interconnect package, etc.), system package (SIP), chip system (SOC).

Ke au o ka pūʻolo lC (13)

Hoʻokaʻawale nui ʻia nā ʻano o ka pāpaʻi 3D i ʻekolu mau ʻāpana: kanu ʻia (ke kanu ʻana i ka hāmeʻa i loko o ka uwila multi-layer a kanu ʻia paha i loko o ka substrate), ʻano substrate ikaika (hoʻohui wafer silicon: hoʻohui mua i nā ʻāpana a me ka substrate wafer e hana i kahi substrate ikaika. ; a laila hoʻonohonoho i nā laina hoʻohui like ʻole, a hoʻohui i nā ʻāpana ʻē aʻe a i ʻole nā ​​​​mea ʻē aʻe ma ka papa luna) a me ke ʻano hoʻopaʻa ʻia (nā wafers silicon i hoʻopaʻa ʻia me ke silika. nā ʻōpala, nā ʻāpana i hoʻopaʻa ʻia me nā ʻāpana silika, a me nā ʻāpana i hoʻopaʻa ʻia me nā ʻāpana).

Ke au o ka pūʻolo lC (8)

ʻO nā ʻano hana hoʻohui 3D e pili ana i ka hoʻopaʻa ʻana i ka uea (WB), flip chip (FC), ma o ke silikona ma o (TSV), ke alakaʻi kiʻiʻoniʻoni, etc.

Hoʻomaopopo ʻo TSV i ka pilina paʻa ma waena o nā pahu. No ka mea ʻoi aku ka pōkole o ka laina interconnection a me ka ikaika kiʻekiʻe, ʻoi aku ka maʻalahi o ka hoʻomaopopo ʻana i ka miniaturization, kiʻekiʻe kiʻekiʻe, hana kiʻekiʻe, a me ka multifunctional heterogeneous structure packaging. I ka manawa like, hiki iā ia ke hoʻopili i nā ʻāpana o nā mea like ʻole;

i kēia manawa, aia ʻelua ʻano o nā ʻenehana hana microelectronics e hoʻohana ana i ke kaʻina TSV: ʻekolu-dimensional circuit packaging (3D IC integration) a me ʻekolu-dimensional silicon packaging (3D Si integration).

ʻO ka ʻokoʻa ma waena o nā ʻano ʻelua:

(1) Pono e hoʻomākaukau ʻia nā electrodes 3D i loko o nā puʻupuʻu, a ua hoʻopili ʻia nā puʻupuʻu (hoʻopaʻa ʻia e ka hoʻopaʻa ʻana, fusion, welding, a me nā mea ʻē aʻe), ʻoiai ʻo 3D silicon packaging kahi pilina pololei ma waena o nā pōpoki (ka hoʻopaʻa ʻana ma waena o nā oxides a me Cu. -Cu pili).

(2) Hiki ke hoʻokō ʻia ka ʻenehana hoʻohui kaapuni 3D ma o ka hoʻopaʻa ʻana ma waena o nā wafers (3D circuit packaging, 3D silicon packaging), ʻoiai ʻo ka paʻa chip-to-chip a me ka chip-to-wafer hoʻopaʻa ʻia e hiki ke hoʻokō wale ʻia e 3D circuit packaging.

(3) Aia nā āpau ma waena o nā ʻāpana i hoʻohui ʻia e ka 3D circuit packaging process, a pono e hoʻopiha ʻia nā mea dielectric e hoʻoponopono i ka conductivity thermal a me ka hoʻonui ʻana o ka wela o ka ʻōnaehana e hōʻoia i ka paʻa o nā waiwai mechanical a me nā uila o ka ʻōnaehana; ʻaʻohe wahi āpau ma waena o nā ʻāpana i hoʻohui ʻia e ka 3D silicon packaging process, a ʻo ka hoʻohana ʻana i ka mana, ka leo, a me ke kaumaha o ka chip he liʻiliʻi, a ʻoi aku ka maikaʻi o ka hana uila.

Ke au o ka pūʻolo lC (10)

Hiki i ke kaʻina hana TSV ke kūkulu i kahi ala hōʻailona kūpaʻa ma o ka substrate a hoʻohui i ka RDL ma luna a ma lalo o ka substrate e hana i kahi ala conductor ʻekolu. No laila, ʻo ke kaʻina hana TSV kekahi o nā pōhaku kihi koʻikoʻi no ke kūkulu ʻana i kahi ʻōnaehana passive ʻekolu-dimensional.

E like me ke kauoha ma waena o ka laina mua (FEOL) a me ka hope hope o ka laina (BEOL), hiki ke hoʻokaʻawale ʻia ke kaʻina hana TSV i ʻekolu kaʻina hana nui, ʻo ia hoʻi, ma mua (ViaFirst), ma waena (Via Middle) a ma ke kaʻina hana hope (Via Last), e like me ka mea i hōʻike ʻia ma ke kiʻi.

Ke au o ka pūʻolo lC (9)

1. Via kaʻina hana etching

ʻO ke kaʻina hana etching ke kī i ka hana ʻana i ka hoʻolālā TSV. Ke koho ʻana i kahi kaʻina hana etching kūpono hiki ke hoʻomaikaʻi maikaʻi i ka ikaika mechanical a me nā waiwai uila o TSV, a pili hou aku i ka hilinaʻi holoʻokoʻa o nā mea ʻekolu-dimensional TSV.

I kēia manawa, ʻehā mau TSV koʻikoʻi ma o nā kaʻina hana etching: Deep Reactive Ion Etching (DRIE), wet etching, photo-assisted electrochemical etching (PAECE) a me laser drilling.

(1) Deep Reactive Ion Etching (DRIE)

Deep reactive ion etching, ʻike ʻia hoʻi ʻo DRIE kaʻina, ʻo ia ke kaʻina hana etching TSV maʻamau, i hoʻohana nui ʻia e ʻike i ka TSV ma o nā hale me ka lākiō kiʻekiʻe. Hiki i nā kaʻina hana etching plasma kuʻuna ke loaʻa i kahi hohonu etching o kekahi mau microns, me ka helu etching haʻahaʻa a me ka nele o ka koho koho mask etching. Ua hana ʻo Bosch i nā hoʻomaikaʻi kaʻina hana ma kēia kumu. Ma ka hoʻohana ʻana iā SF6 ma ke ʻano he kinoea reactive a me ka hoʻokuʻu ʻana i ke kinoea C4F8 i ka wā o ke kaʻina hana etching ma ke ʻano he pale passivation no nā ʻaoʻao ʻaoʻao, ua kūpono ke kaʻina hana DRIE no ka etching kiʻekiʻe aspect ratio vias. No laila, kapa ʻia ʻo ia ʻo ke kaʻina Bosch ma hope o kāna mea hana.

ʻO ke kiʻi ma lalo nei he kiʻi o kahi lākiō hiʻohiʻona kiʻekiʻe ma o ke kālai ʻana i ke kaʻina hana DRIE.

Ke au o ka pūʻolo lC (5)

ʻOiai ua hoʻohana nui ʻia ke kaʻina hana DRIE i ke kaʻina TSV ma muli o kona mana maikaʻi, ʻo kona hemahema ʻo ia ka ʻilihune o ka palahalaha ʻaoʻao a e hoʻokumu ʻia nā hemahema wrinkle. ʻOi aku ke koʻikoʻi o kēia hemahema i ka wā e kālai ana i ka lākiō hiʻohiʻona vias.

(2) ʻAi pulu

Hoʻohana ka wet etching i ka hui pū ʻana o ka mask a me ke kiʻi kemika e kālai ai ma nā lua. ʻO ka hopena etching maʻamau i hoʻohana ʻia ʻo KOH, hiki ke hoʻopaʻa i nā kūlana ma luna o ka substrate silicon i pale ʻole ʻia e ka mask, a laila e hoʻokumu ʻia ai ke ʻano o ka lua i makemake ʻia. ʻO ke kālai pulu ka hana mua loa i kūkulu ʻia. Ma muli o ka maʻalahi o kāna kaʻina hana a me nā mea pono e pono ai, kūpono ia no ka hana nui o TSV ma ke kumu kūʻai haʻahaʻa. Eia naʻe, ua hoʻoholo kona ʻano etching kemika e hoʻopili ʻia ka puka puka i hana ʻia e kēia ʻano hana e ke ʻano aniani o ka wafer silicon, e hana ana i ka etched through-hole non-vertical akā e hōʻike ana i kahi ʻano maopopo o ka laulā luna a me ka haiki lalo. Hoʻopili kēia hemahema i ka hoʻohana ʻana i ka etching pulu i ka hana TSV.

(3) Etching electrochemical kōkua kiʻi (PAECE)

ʻO ke kumu kumu o ke kiʻi kōkua kiʻi electrochemical etching (PAECE) ʻo ia ka hoʻohana ʻana i ke kukui ultraviolet e hoʻolalelale i ka hana ʻana o nā lua electron-hole, a laila e hoʻolalelale i ke kaʻina hana etching electrochemical. Hoʻohālikelike ʻia me ke kaʻina hana DRIE i hoʻohana nui ʻia, ʻoi aku ka maikaʻi o ke kaʻina PAECE no ka etching ultra-large hiʻona lākiō ma waena o nā hale puka i ʻoi aku ma mua o 100: 1, akā ʻo kona hemahema, ʻoi aku ka nāwaliwali o ka hohonu o ka etching ma mua o DRIE, a hiki i kāna ʻenehana. makemake hou i ka noiʻi a me ka hoʻomaikaʻi kaʻina hana.

Ke au o ka pūʻolo lC (6)

(4) ʻO ka hoʻoheheʻe laser

He ʻokoʻa mai nā ʻano ʻekolu i luna. ʻO ke ʻano hana hoʻoheheʻe laser he ʻano hana kino maoli. Hoʻohana nui ia i ka irradiation laser ikaika nui e hoʻoheheʻe a hoʻoheheʻe i ka mea substrate ma ka wahi i ʻōlelo ʻia e ʻike kino ai i ke kūkulu ʻana o TSV.

ʻO ka puka puka i hana ʻia e ka wili ʻana i ka laser he ʻano kiʻekiʻe ke kiʻekiʻe a ʻo ka ʻaoʻao ʻaoʻao ke kū pololei. Eia nō naʻe, no ka hoʻohana maoli ʻana o ka hoʻoheheʻe laser i ka hoʻomehana kūloko e hana i ka puka ma waena, e hoʻopilikia maikaʻi ʻia ka pā puka o TSV e ka pōʻino wela a hoʻemi i ka hilinaʻi.

Ke au o ka pūʻolo lC (11)

2. Ke kaʻina hoʻopaʻa ʻana o ka papa liner

ʻO kekahi ʻenehana koʻikoʻi no ka hana ʻana i ka TSV, ʻo ia ke kaʻina hoʻopaʻa ʻana o ka liner layer.

Hana ʻia ke kaʻina hana deposition layer liner ma hope o ke kālai ʻia ʻana o ka puka puka. ʻO ka papa liner i waiho ʻia he oxide e like me SiO2. Aia ka papa liner ma waena o ka conductor o loko o ka TSV a me ka substrate, a ke pāʻani nui nei i ke kuleana o ka hoʻokaʻawale ʻana i ka leakage o kēia manawa DC. Ma waho aʻe o ka waiho ʻana i ka oxide, koi ʻia ka pale a me nā papa hua no ka hoʻopiha conductor i ke kaʻina hana aʻe.

Pono ka papa liner i hana ʻia i nā koi kumu ʻelua:

(1) pono e hoʻokō ka voltage haʻihaʻi o ka papa insulating i nā koi hana maoli o TSV;

(2) paʻa loa nā papa i waiho ʻia a pili maikaʻi kekahi i kekahi.

Hōʻike kēia kiʻi i ke kiʻi o ka papa liner i waiho ʻia e ka plasma enhanced chemical vapor deposition (PECVD).

Ke au o ka pūʻolo lC (1)

Pono e hoʻoponopono ʻia ke kaʻina hana deposition no nā kaʻina hana TSV like ʻole. No ke kaʻina hana ma mua o ka puka, hiki ke hoʻohana ʻia kahi kaʻina deposition wela kiʻekiʻe e hoʻomaikaʻi i ka maikaʻi o ka papa oxide.

Hiki ke ho'okumu 'ia ka waiho 'ana o ka wela ki'eki'e ma luna o ka tetraethyl orthosilicate (TEOS) i hui pū 'ia me ke ka'ina ho'ohāhā wela e hana ai i kahi papa insulating SiO2 kūlana ki'eki'e. No ke kaʻina hana ma waena o ka lua a me hope, no ka mea ua hoʻopau ʻia ke kaʻina BEOL i ka wā o ka waiho ʻana, pono ke ʻano haʻahaʻa haʻahaʻa e hōʻoia i ka hoʻohālikelike ʻana me nā mea BEOL.

Ma lalo o kēia kūlana, pono e kaupalena ʻia ka mahana deposition i 450 °, me ka hoʻohana ʻana o PECVD e waiho iā SiO2 a i ʻole SiNx ma ke ʻano he insulating layer.

ʻO kekahi ʻano hana maʻamau, ʻo ia ka hoʻohana ʻana i ka deposition layer atomic (ALD) e waiho iā Al2O3 no ka loaʻa ʻana o kahi papa insulating denser.

3. Kaʻina hana hoʻopiha metala

Hoʻokō koke ʻia ke kaʻina hana hoʻopiha TSV ma hope o ke kaʻina deposition liner, ʻo ia kekahi ʻenehana koʻikoʻi e hoʻoholo ai i ka maikaʻi o TSV.

ʻO nā mea hiki ke hoʻopiha ʻia me ka doped polysilicon, tungsten, carbon nanotubes, a me nā mea ʻē aʻe ma muli o ke kaʻina hana i hoʻohana ʻia, akā ʻo ka mea nui loa he keleawe electroplated, no ka mea, ua oʻo kāna kaʻina hana a ʻoi aku ka kiʻekiʻe o kāna conductivity uila a me ka wela.

Wahi a ka hoʻokaʻawale ʻana o kāna helu electroplating i loko o ka lua, hiki ke hoʻokaʻawale ʻia i nā ʻano subconformal, conformal, superconformal a me lalo-up electroplating, e like me ka mea i hōʻike ʻia ma ke kiʻi.

Ke au o ka pūʻolo lC (4)

Ua hoʻohana nui ʻia ka subconformal electroplating i ka wā mua o ka noiʻi TSV. E like me ka hōʻike ʻana ma ke Kiʻi (a), ʻoi aku ka nui o nā Cu i hāʻawi ʻia e ka electrolysis ma luna, ʻoiai ʻaʻole i hoʻonui ʻia ka lalo, kahi e ʻoi aku ka kiʻekiʻe o ka helu electroplating ma luna o ka puka ma lalo o luna. No laila, e pani ʻia ka piko o ka puka ma mua ma mua o ka hoʻopiha piha ʻana, a e hoʻokumu ʻia kahi hakahaka nui i loko.

Hōʻike ʻia ke kiʻi hoʻolālā a me ke kiʻi o ke ʻano electroplating conformal ma ke Kiʻi (b). Ma ka hōʻoia ʻana i ka hoʻohui like ʻana o nā ion Cu, ʻo ka helu electroplating ma kēlā me kēia kūlana i loko o ka puka ma waena o ka lua, no laila e waiho ʻia kahi humuhumu i loko, a ʻoi aku ka liʻiliʻi o ka leo ʻole ma mua o ke ʻano subconformal electroplating, no laila. hoohana nui ia.

I mea e hoʻokō hou ai i kahi hopena hoʻopiha piha ʻole, ua manaʻo ʻia ke ʻano electroplating superconformal e hoʻonui i ke ʻano electroplating conformal. E like me ka mea i hōʻike ʻia ma ke Kiʻi (c), ma ka hoʻomalu ʻana i ka hoʻolako ʻana i nā iona Cu, ʻoi aku ka kiʻekiʻe o ka hoʻopiha piha ʻana ma lalo ma mua o kēlā ma nā kūlana ʻē aʻe, no laila e hoʻomaikaʻi i ka ʻanuʻu ʻanuʻu o ka hoʻopiha piha mai lalo a luna e hoʻopau loa i ke kaʻina i waiho ʻia. e ke ʻano electroplating conformal, i mea e hoʻokō ai i ka hoʻopiha keleawe metala ʻole ʻole.

Hiki ke noʻonoʻo ʻia ke ʻano hana electroplating lalo i kahi hihia kūikawā o ke ʻano super-conformal. I kēia hihia, ua kāohi ʻia ka helu electroplating koe ka lalo i ka ʻole, a ʻo ka electroplating wale nō e lawe mālie ʻia mai lalo a luna. Ma kahi o ka pono kīnā ʻole o ke ʻano electroplating conformal, hiki i kēia ʻano hana ke hōʻemi pono i ka manawa electroplating holoʻokoʻa, no laila ua aʻo nui ʻia i nā makahiki i hala.

4. ʻenehana hana RDL

ʻO ke kaʻina hana RDL he ʻenehana kumu pono ʻole i ke kaʻina hana hoʻopihapiha ʻekolu. Ma o kēia kaʻina hana, hiki ke hana ʻia nā pilina metala ma nā ʻaoʻao ʻelua o ka substrate e hoʻokō i ke kumu o ka hoʻohele hou ʻana a i ʻole ka pilina ma waena o nā pūʻolo. No laila, hoʻohana nui ʻia ke kaʻina hana RDL i nā ʻōnaehana hoʻopihapiha fan-in-fan-out a i ʻole 2.5D/3D.

Ma ke kaʻina hana ʻana i nā mea hana ʻekolu-dimensional, hoʻohana mau ʻia ke kaʻina RDL no ka hoʻopili ʻana iā TSV e ʻike i nā ʻano hana ʻekolu-dimensional.

Aia i kēia manawa ʻelua kaʻina hana RDL koʻikoʻi. Hoʻokumu ʻia ka mea mua ma nā polymers photosensitive a hui pū ʻia me ka electroplating keleawe a me nā kaʻina hana etching; ua hoʻokō ʻia kekahi ma ka hoʻohana ʻana i ke kaʻina hana Cu Damascus i hui pū ʻia me ka PECVD a me ke kaʻina hana chemical polishing (CMP).

E hōʻike ana kēia i nā ala kaʻina hana nui o kēia mau RDL ʻelua.

Ke au o ka pūʻolo lC (12)

Hōʻike ʻia ke kaʻina RDL e pili ana i ka polymer photosensitive ma ke kiʻi ma luna.

ʻO ka mea mua, ua uhi ʻia kahi papa o PI a i ʻole BCB glue ma luna o ka ʻili o ka wafer ma o ka hoʻololi ʻana, a ma hope o ka hoʻomehana ʻana a me ka hoʻōla ʻana, hoʻohana ʻia kahi kaʻina photolithography e wehe i nā puka ma kahi i makemake ʻia, a laila hana ʻia ke etching. A laila, ma hope o ka wehe 'ana i ka photoresist, ua sputtered Ti a me Cu ma luna o ka wafer ma o ke kino mahu mahu deposition kaʻina (PVD) ma ke 'ano he papa pale a me ka anoano papa, pakahi. A laila, hana ʻia ka papa mua o RDL ma ka papa Ti / Cu i hōʻike ʻia ma o ka hoʻohui ʻana i ka photolithography a me nā kaʻina hana electroplating Cu, a laila wehe ʻia ka photoresist a hoʻopau ʻia ka nui o Ti a me Cu. E hana hou i nā ʻanuʻu i luna e hana i kahi hoʻolālā RDL multi-layer. Hoʻohana nui ʻia kēia ʻano hana i ka ʻoihana.

ʻO kekahi ʻano hana ʻē aʻe no ka hana ʻana i ka RDL e hoʻokumu nui ʻia ma ke kaʻina Cu Damascus, kahi e hui pū ai i nā kaʻina PECVD a me CMP.

ʻO ka ʻokoʻa ma waena o kēia ʻano hana a me ke kaʻina RDL e pili ana i ka polymer photosensitive ʻo ia i ka hana mua o ka hana ʻana i kēlā me kēia papa, hoʻohana ʻia ʻo PECVD e waiho iā SiO2 a i ʻole Si3N4 ma ke ʻano he insulating layer, a laila hana ʻia kahi puka makani ma ka papa insulating e photolithography a reactive ion etching, a me Ti/Cu barrier/seed layer a me conductor copper is sputtered each, and then the conductor layer is thinned to the required thickness by ʻO ke kaʻina hana CMP, ʻo ia hoʻi, hoʻokumu ʻia kahi papa o RDL a i ʻole ma waena o ka lua.

ʻO ke kiʻi ma lalo nei he kiʻi schematic a me ke kiʻi o ka ʻāpana keʻa o kahi RDL multi-layer i kūkulu ʻia ma muli o ke kaʻina Cu Damascus. Hiki ke ʻike ʻia ua hoʻopili mua ʻia ʻo TSV i ka papa ma waena o ka puka V01, a laila hoʻopaʻa ʻia mai lalo a luna ma ke ʻano o RDL1, ma waena o ka lua V12, a me RDL2.

Hana ʻia kēlā me kēia papa o RDL a i ʻole ma waena o ka lua i ke kaʻina e like me ke ʻano o luna.Ma muli o ke kaʻina hana RDL e pono ai ka hoʻohana ʻana i ke kaʻina CMP, ʻoi aku ka kiʻekiʻe o kāna kumukūʻai hana ma mua o ke kaʻina RDL e pili ana i ka polymer photosensitive, no laila he haʻahaʻa loa kāna noi.

Ke au o ka pūʻolo lC (2)

5. ʻenehana hana IPD

No ka hana ʻana i nā mea hana ʻekolu-dimensional, ma waho aʻe o ka hoʻopili pololei ʻana ma luna o ka chip ma MMIC, hāʻawi ke kaʻina IPD i kahi ala ʻenehana ʻoi aku ka maʻalahi.

ʻO nā mea hana passive i hoʻohui ʻia, ʻike ʻia ʻo IPD kaʻina, hoʻohui i kekahi hui o nā mea passive me nā inductors on-chip, capacitors, resistors, balun converters, etc. e kapa ʻia e like me nā koi hoʻolālā.

No ka mea ma ke kaʻina hana IPD, hana ʻia nā mea passive a hoʻopili pololei ʻia ma ka papa hoʻoili, ʻoi aku ka maʻalahi o ke kahe o ke kaʻina hana ma mua o ka hoʻohui ʻana i ka chip IC, a hiki ke hana nui ʻia ma mua e like me ka hale waihona puke passive.

No ka hana ʻana i nā mea hana passive ʻekolu-dimensional TSV, hiki i ka IPD ke hoʻopau maikaʻi i ke kaumaha o ke kumukūʻai o nā kaʻina hana hoʻopihapiha ʻekolu-dimensional me TSV a me RDL.

Ma waho aʻe o nā pono kumukūʻai, ʻo kahi pono ʻē aʻe o ka IPD ʻo kona maʻalahi kiʻekiʻe. Hōʻike ʻia kekahi o ka maʻalahi o ka IPD i nā ʻano hoʻohui like ʻole, e like me ka mea i hōʻike ʻia ma ke kiʻi ma lalo nei. Ma waho aʻe o nā ʻano kumu ʻelua o ka hoʻopili pololei ʻana i ka IPD i loko o ka substrate pōʻai ma o ke kaʻina hana flip-chip e like me ka mea i hōʻike ʻia ma ke Kiʻi (a) a i ʻole ke kaʻina hana hoʻopaʻa e like me ka hōʻike ʻana ma ke Kiʻi (b), hiki ke hoʻohui ʻia kekahi papa o IPD ma kahi papa hoʻokahi. o IPD e like me ia i hōʻike ʻia ma nā Kiʻi (c)-(e) no ka loaʻa ʻana o kahi ākea ākea o ka hui ʻana o nā mīkini passive.

I ka manawa like, e like me ka mea i hōʻike ʻia ma ke Kiʻi (f), hiki ke hoʻohana hou ʻia ka IPD ma ke ʻano he papa adapter e kanu pololei i ka chip i hoʻohui ʻia ma luna o ia mea e kūkulu pono i kahi ʻōnaehana hoʻopihapiha kiʻekiʻe.

Ke au o ka pūʻolo lC (7)

I ka hoʻohana ʻana i ka IPD e kūkulu i ʻekolu-dimensional passive device, hiki ke hoʻohana ʻia ke kaʻina TSV a me ke kaʻina RDL. ʻO ke kahe kaʻina hana he mea like ia me ka mea i ʻōlelo ʻia ma luna o ke kaʻina hana hoʻohuihui, ʻaʻole e hana hou ʻia; ʻO ka ʻokoʻa, ʻoiai ua hoʻololi ʻia ka mea hoʻohui mai ka chip a hiki i ka adapter board, ʻaʻohe pono e noʻonoʻo i ka hopena o ke kaʻina hana hoʻopihapiha ʻekolu-dimensional ma ka wahi hana a me ka papa interconnection. Ke alakaʻi hou aku nei kēia i kahi maʻalahi o ka IPD: hiki ke koho maʻalahi i nā ʻano mea substrate e like me nā koi hoʻolālā o nā mea passive.

ʻO nā mea substrate i loaʻa no ka IPD, ʻaʻole wale nā ​​mea semiconductor substrate maʻamau e like me Si a me GaN, akā ʻo Al2O3 ceramics, haʻahaʻa haʻahaʻa / kiʻekiʻe-mahana co-fire ceramics, aniani substrates, etc. nā mea i hoʻohui ʻia e IPD.

No ka laʻana, hiki ke hoʻohana ʻia ka hoʻolālā passive inductor ʻekolu-dimensional i hoʻohui ʻia e IPD i kahi pani aniani e hoʻomaikaʻi maikaʻi i ka hana o ka inductor. He ʻokoʻa i ka manaʻo o TSV, ua kapa ʻia nā puka-puka i hana ʻia ma luna o ke aniani substrate ma o ke aniani vias (TGV). Hōʻike ʻia ke kiʻi o ka inductor ʻekolu-dimensional i hana ʻia ma muli o nā kaʻina IPD a me TGV ma ke kiʻi ma lalo nei. No ka mea, ʻoi aku ka kiʻekiʻe o ka resistivity o ka substrate aniani ma mua o nā mea semiconductor maʻamau e like me Si, ʻoi aku ka liʻiliʻi o ka TGV ʻekolu-dimensional inductor, a ʻoi aku ka liʻiliʻi o ka hoʻokomo ʻana e ka hopena parasitic substrate ma nā alapine kiʻekiʻe ma mua o ka ka TSV ekolu-dimensional inductor.

Ke au o ka pūʻolo lC (3)

 

Ma ka lima 'ē aʻe, metala-insulator-metala (MIM) hiki ke hana 'ia ma ke aniani substrate IPD ma o ka lahilahi kiʻiʻoniʻoni deposition kaʻina hana, a interconnected me ka TGV ekolu-dimensional inductor e hana i ekolu-dimensional passive kānana ana. No laila, ʻo ke kaʻina IPD he hiki ke hoʻohana ākea no ka hoʻomohala ʻana i nā mea hana passive ʻekolu-dimensional hou.


Ka manawa hoʻouna: Nov-12-2024